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Page 2

DDigitaligital P Principlesrinciples

andand

Logic DesignLogic Design

Page 253

238 DIGITAL PRINCIPLES AND LOGIC DESIGN

Figure 7.49 General model for conversion of one type of fl ip-fl op to another type

7.11.1 Conversion of an S-R Flip-� op to a D Flip-� op

The excitation tables of S-R and D fl ip-fl ops are given in the table in Figure 7.48 from
which we make the truth table given in Figure 7.50.

FF data inputs Output S-R FF inputs

D Q S R

0 0 0 X

1 0 1 0

0 1 0 1

1 1 X 0

Figure 7.50

From the table in Figure 7.50, we make the Karnaugh maps for inputs S and R as
shown in Figure 7.51(a) and Figure 7.51(b).

Figure 7.51(a) Figure 7.51(b)

Simplifying with the help of the Karnaugh maps, we obtain S = D and R = D'.

Hence the circuit may be designed as in Figure 7.52.

Figure 7.52 A D fl ip-fl op using an S-R fl ip-fl op.

F lip-flop
convers ion

log ic

G iven
F lip-flop

Q
F lip-flop

Q '
Data Inpu ts

0 0

X1

0

0

1

1
Q

D

D

For S

X 1

00

0

0

1

1
Q

D '

D

For R

Q

Q '

D S

R

Page 254

SEQUENTIAL LOGIC CIRCUITS 239

7.11.2 Conversion of an S-R Flip-� op to a J-K Flip-� op

The excitation tables of S-R and J-K fl ip-fl ops are given in the table in Figure 7.48
from which we make the truth table given in Figure 7.53.

FF data inputs Output S-R FF inputs

J K Q S R

0 0 0 0 X

0 1 0 0 X

1 0 0 1 0

1 1 0 1 0

0 1 1 0 1

1 1 1 0 1

0 0 1 X 0

1 0 1 X 0

Figure 7.53

From the truth table in Figure 7.53, the Karnaugh map is prepared as shown in Figure
7.54(a) and Figure 7.54(b).

Figure 7.54(a) Figure 7.54(b)

Hence we get the Boolean expression for S and R as

S = JQ'

and R = KQ.

Hence the circuit may be realized as in Figure 7.55.

Figure 7.55 A J-K fl ip-fl op using an S-R fl ip-fl op.

0 X 0 0

10X1

00

0

1

01 11 10
KQ

J

JQ '

F or S

X 0 1 X

0100

00

0

1

01 11 10
KQ

J

KQ

For R

1

2
K

J
QS

Q 'R

Page 506

INDEX 491

G

Gate 59, 67, 77, 86

Graphic symbol 68, 69

Gray 33, 34, 45, 49

Gray code 33, 34, 45, 49

H

Hexadecimal 2, 3, 11, 25

Hexadecimal code 2

Hexadecimal numbers 4, 9

Huntington postulates 53, 54, 55

I

Identity element 52, 54, 55

Interfacing 390, 423

Inverse 52

J

Johnson 277, 278, 279

Johnson counter 277, 278, 279

K

Karnaugh map 89, 90, 110, 124

L

Level triggering 236

Literal 59, 77, 78

M

Map method 89, 103, 111, 124

Minuend 14, 15, 25

Moebius counter 278

N

NAND 67, 68, 77, 87

NAND gate 70, 71, 79, 85

Negative logic 83, 84

Nondegenerate forms 77

NOR 79, 87

NOR gate 70, 71, 81, 85

NOT 54, 58, 68, 73

O

Octal numbers 8, 9

P

PLA 194, 202, 203, 213

PLA program table 204, 205, 206, 207

PLD 193, 194, 211, 212

Positive logic 83, 84

Postulates 51, 53, 54, 55, 64

Product of maxterms 63, 66, 87

Product of sums 60, 63, 65, 87

Product terms 60, 61, 65

Programmable 193, 194, 208, 213

Q

Quine-McCluskey method 103, 106

R

R’s complement 10, 11, 14

Read Only Memory 194, 195, 201

Register 263, 264, 285, 289

Ring 277, 278, 279, 289

Ring counter 276, 277, 289

S

Serial addition 283

Shift left 275, 276

Shift register 263, 264, 279, 289

Shift right 271, 272, 275

Sign bit 19, 20

Simplifi cation 59, 84, 85

Specifi cation 355, 371

Standard forms 60

Standard product 60, 61

Standard sum 63

Subtraction 10, 13, 15, 29, 30

Successive approximation type 363, 365, 376

Sum of minterms 66, 87

Sum of products 60, 62, 77

Page 507

492 DIGITAL PRINCIPLES AND LOGIC DESIGN

T

Tabulation method 103, 106, 123

Types of 201, 211, 212

U

Universal 70, 71,

Universal gates 70, 71, 85

V

Voltage to time conversion 370

W

Wired 76, 77

Wired logic 76, 77

With NOR 74, 75, 81

With ROM 198, 199

Word 195, 202

X

XOR 68, 69, 85

XNOR 68, 69, 70

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