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TitlePci Express System Architecture
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Table of Contents
                            [Trial version] Main Page
[Trial version] Table of content
[Trial version] Copyright
[Trial version] Figures
[Trial version] Tables
[Trial version] Acknowledgments
[Trial version] About This Book
	[Trial version] The MindShare Architecture Series
	[Trial version] Cautionary Note
	[Trial version] Intended Audience
	[Trial version] Prerequisite Knowledge
	[Trial version] Topics and Organization
	[Trial version] Documentation Conventions
	[Trial version] Visit Our Web Site
	[Trial version] We Want Your Feedback
[Trial version] Part One: The Big Picture
	[Trial version] Chapter 1. Architectural Perspective
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Introduction To PCI Express
		[Trial version] Predecessor Buses Compared
		[Trial version] I/O Bus Architecture Perspective
		[Trial version] The PCI Express Way
		[Trial version] PCI Express Specifications
	[Trial version] Chapter 2. Architecture Overview
		[Trial version] Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Introduction to PCI Express Transactions
		[Trial version] PCI Express Device Layers
		[Trial version] Example of a Non-Posted Memory Read Transaction
		[Trial version] Hot Plug
		[Trial version] PCI Express Performance and Data Transfer Efficiency
[Trial version] Part Two: Transaction Protocol
	[Trial version] Chapter 3. Address Spaces & Transaction Routing
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Introduction
		[Trial version] Two Types of Local Link Traffic
		[Trial version] Transaction Layer Packet Routing Basics
		[Trial version] Applying Routing Mechanisms
		[Trial version] Plug-And-Play Configuration of Routing Options
	[Trial version] Chapter 4. Packet-Based Transactions
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Introduction to the Packet-Based Protocol
		[Trial version] Transaction Layer Packets
		[Trial version] Data Link Layer Packets
	[Trial version] Chapter 5. ACK/NAK Protocol
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Reliable Transport of TLPs Across Each Link
		[Trial version] Elements of the ACK/NAK Protocol
		[Trial version] ACK/NAK DLLP Format
		[Trial version] ACK/NAK Protocol Details
		[Trial version] Error Situations Reliably Handled by ACK/NAK Protocol
		[Trial version] ACK/NAK Protocol Summary
		[Trial version] Recommended Priority To Schedule Packets
		[Trial version] Some More Examples
		[Trial version] Switch Cut-Through Mode
	[Trial version] Chapter 6. QoS/TCs/VCs and Arbitration
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Quality of Service
		[Trial version] Perspective on QOS/TC/VC and Arbitration
		[Trial version] Traffic Classes and Virtual Channels
		[Trial version] Arbitration
	[Trial version] Chapter 7. Flow Control
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Flow Control Concept
		[Trial version] Flow Control Buffers
		[Trial version] Introduction to the Flow Control Mechanism
		[Trial version] Flow Control Packets
		[Trial version] Operation of the Flow Control Model - An Example
		[Trial version] Infinite Flow Control Advertisement
		[Trial version] The Minimum Flow Control Advertisement
		[Trial version] Flow Control Initialization
		[Trial version] Flow Control Updates Following FC_INIT
	[Trial version] Chapter 8. Transaction Ordering
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Introduction
		[Trial version] Producer/Consumer Model
		[Trial version] Native PCI Express Ordering Rules
		[Trial version] Relaxed Ordering
		[Trial version] Modified Ordering Rules Improve Performance
		[Trial version] Support for PCI Buses and Deadlock Avoidance
	[Trial version] Chapter 9. Interrupts
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Two Methods of Interrupt Delivery
		[Trial version] Message Signaled Interrupts
		[Trial version] Legacy PCI Interrupt Delivery
		[Trial version] Devices May Support Both MSI and Legacy Interrupts
		[Trial version] Special Consideration for Base System Peripherals
	[Trial version] Chapter 10. Error Detection and Handling
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Background
		[Trial version] Introduction to PCI Express Error Management
		[Trial version] Sources of PCI Express Errors
		[Trial version] Error Classifications
		[Trial version] How Errors are Reported
		[Trial version] Baseline Error Detection and Handling
		[Trial version] Advanced Error Reporting Mechanisms
		[Trial version] Summary of Error Logging and Reporting
[Trial version] Part Three: The Physical Layer
	[Trial version] Chapter 11. Physical Layer Logic
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Physical Layer Overview
		[Trial version] Transmit Logic Details
		[Trial version] Receive Logic Details
		[Trial version] Physical Layer Error Handling
	[Trial version] Chapter 12. Electrical Physical Layer
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Electrical Physical Layer Overview
		[Trial version] High Speed Electrical Signaling
		[Trial version] LVDS Eye Diagram
		[Trial version] Transmitter Driver Characteristics
		[Trial version] Input Receiver Characteristics
		[Trial version] Electrical Physical Layer State in Power States
	[Trial version] Chapter 13. System Reset
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Two Categories of System Reset
		[Trial version] Reset Exit
		[Trial version] Link Wakeup from L2 Low Power State
	[Trial version] Chapter 14. Link Initialization & Training
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Link Initialization and Training Overview
		[Trial version] Ordered-Sets Used During Link Training and Initialization
		[Trial version] Link Training and Status State Machine (LTSSM)
		[Trial version] Detailed Description of LTSSM States
		[Trial version] LTSSM Related Configuration Registers
[Trial version] Part Four: Power-Related Topics
	[Trial version] Chapter 15. Power Budgeting
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Introduction to Power Budgeting
		[Trial version] The Power Budgeting Elements
		[Trial version] Slot Power Limit Control
		[Trial version] The Power Budget Capabilities Register Set
	[Trial version] Chapter 16. Power Management
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Introduction
		[Trial version] Primer on Configuration Software
		[Trial version] Function Power Management
		[Trial version] Introduction to Link Power Management
		[Trial version] Link Active State Power Management
		[Trial version] Software Initiated Link Power Management
		[Trial version] Link Wake Protocol and PME Generation
[Trial version] Part Five: Optional Topics
	[Trial version] Chapter 17. Hot Plug
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Background
		[Trial version] Hot Plug in the PCI Express Environment
		[Trial version] Elements Required to Support Hot Plug
		[Trial version] Card Removal and Insertion Procedures
		[Trial version] Standardized Usage Model
		[Trial version] Standard Hot Plug Controller Signaling Interface
		[Trial version] The Hot-Plug Controller Programming Interface
		[Trial version] Slot Numbering
		[Trial version] Quiescing Card and Driver
		[Trial version] The Primitives
	[Trial version] Chapter 18. Add-in Cards and Connectors
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Introduction
		[Trial version] Form Factors Under Development
[Trial version] Part Six: PCI Express Configuration
	[Trial version] Chapter 19. Configuration Overview
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Definition of Device and Function
		[Trial version] Definition of Primary and Secondary Bus
		[Trial version] Topology Is Unknown At Startup
		[Trial version] Each Function Implements a Set of Configuration Registers
		[Trial version] Host/PCI Bridge's Configuration Registers
		[Trial version] Configuration Transactions Are Originated by the Processor
		[Trial version] Configuration Transactions Are Routed Via Bus, Device, and Function Number
		[Trial version] How a Function Is Discovered
		[Trial version] How To Differentiate a PCI-to-PCI Bridge From a Non-Bridge Function
	[Trial version] Chapter 20. Configuration Mechanisms
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Introduction
		[Trial version] PCI-Compatible Configuration Mechanism
		[Trial version] PCI Express Enhanced Configuration Mechanism
		[Trial version] Type 0 Configuration Request
		[Trial version] Type 1 Configuration Request
		[Trial version] Example PCI-Compatible Configuration Access
		[Trial version] Example Enhanced Configuration Access
		[Trial version] Initial Configuration Accesses
	[Trial version] Chapter 21. PCI Express Enumeration
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Introduction
		[Trial version] Enumerating a System With a Single Root Complex
		[Trial version] Enumerating a System With Multiple Root Complexes
		[Trial version] A Multifunction Device Within a Root Complex or a Switch
		[Trial version] An Endpoint Embedded in a Switch or Root Complex
		[Trial version] Memorize Your Identity
		[Trial version] Root Complex Register Blocks (RCRBs)
		[Trial version] Miscellaneous Rules
	[Trial version] Chapter 22. PCI Compatible Configuration Registers
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] Header Type 0
		[Trial version] Header Type 1
		[Trial version] PCI-Compatible Capabilities
	[Trial version] Chapter 23. Expansion ROMs
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] The Next Chapter
		[Trial version] ROM Purpose—Device Can Be Used In Boot Process
		[Trial version] ROM Detection
		[Trial version] ROM Shadowing Required
		[Trial version] ROM Content
		[Trial version] Execution of Initialization Code
		[Trial version] Introduction to Open Firmware
	[Trial version] Chapter 24. Express-Specific Configuration Registers
		[Trial version] The Previous Chapter
		[Trial version] This Chapter
		[Trial version] Introduction
		[Trial version] PCI Express Capability Register Set
		[Trial version] PCI Express Extended Capabilities
		[Trial version] RCRB
[Trial version] Appendices
	[Trial version] Appendix A. Test, Debug and Verification
		[Trial version] Scope
		[Trial version] Serial Bus Topology
		[Trial version] Dual-Simplex
		[Trial version] Setting Up the Analyzer, Capturing and Triggering
		[Trial version] Link Training, the First Step in Communication
		[Trial version] Slot Connector vs. Mid-Bus Pad
		[Trial version] Exercising: In-Depth Verification
		[Trial version] Signal Integrity, Design and Measurement
	[Trial version] Appendix B. Markets & Applications for the PCI Express™ Architecture
		[Trial version] Introduction
		[Trial version] Enterprise Computing Systems
		[Trial version] Embedded Control
		[Trial version] Storage Systems
		[Trial version] Communications Systems
		[Trial version] Summary
	[Trial version] Appendix C. Implementing Intelligent Adapters and Multi-Host Systems With PCI Express™ Technology
		[Trial version] Introduction
		[Trial version] Usage Models
		[Trial version] The History Multi-Processor Implementations Using PCI
		[Trial version] Implementing Multi-host/Intelligent Adapters in PCI Express Base Systems
		[Trial version] Summary
		[Trial version] Address Translation
	[Trial version] Appendix D. Class Codes
	[Trial version] Appendix E. Locked Transactions Series
		[Trial version] Introduction
		[Trial version] Background
		[Trial version] The PCI Express Lock Protocol
		[Trial version] Summary of Locking Rules
[Trial version] Index
	[Trial version] Index SYMBOL
	[Trial version] Index A
	[Trial version] Index B
	[Trial version] Index C
	[Trial version] Index D
	[Trial version] Index E
	[Trial version] Index F
	[Trial version] Index G
	[Trial version] Index H
	[Trial version] Index I
	[Trial version] Index K
	[Trial version] Index L
	[Trial version] Index M
	[Trial version] Index N
	[Trial version] Index O
	[Trial version] Index P
	[Trial version] Index Q
	[Trial version] Index R
	[Trial version] Index S
	[Trial version] Index T
	[Trial version] Index U
	[Trial version] Index V
	[Trial version] Index W
                        
Document Text Contents
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[ Team LiB ]


• Table of Contents
• Index

PCI Express System Architecture
By MindShare, Inc , Ravi Budruk, Don Anderson, Tom Shanley



Publisher: Addison Wesley

Pub Date: September 04, 2003

ISBN: 0-321-15630-7

Pages: 1120

"We have always recommended these books to our customers and even our own engineers for
developing a better understanding of technologies and specifications. We find the latest PCI
Express book from MindShare to have the same content and high quality as all the others."
Nader Saleh, CEO/President, Catalyst Enterprises, Inc.

PCI Express is the third-generation Peripheral Component Inter-connect technology for a wide
range of systems and peripheral devices. Incorporating recent advances in high-speed,
point-to-point interconnects, PCI Express provides significantly higher performance, reliability,
and enhanced capabilities at a lower cost than the previous PCI and PCI-X standards.
Therefore, anyone working on next-generation PC systems, BIOS and device driver
development, and peripheral device design will need to have a thorough understanding of PCI
Express.

PCI Express System Architecture provides an in-depth description and comprehensive
reference to the PCI Express standard. The book contains information needed for design,
verification, and test, as well as background information essential for writing low-level BIOS
and device drivers. In addition, it offers valuable insight into the technology's evolution and
cutting-edge features.

Following an overview of the PCI Express architecture, the book moves on to cover
transaction protocols, the physical/electrical layer, power management, configuration, and
more. Specific topics covered include:

 Split transaction protocol

 Packet format and definition, including use of each field

 ACK/NAK protocol

 Traffic Class and Virtual Channel applications and use

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